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1

Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs

Qiang Zhou, Jin Shi, Bin Liu, Yici Cai

Journal:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Year:

2011

Language:

english

File:

PDF, 544 KB

english, 2011

2

[IEEE 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - Jeju, Korea (South) (2018.1.22-2018.1.25)] 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - ASAX: Automatic security assertion extraction for detecting Hardware Trojans

Wang, Chenguang, Cai, Yici, Zhou, Qiang, Wang, Haoyi

Year:

2018

Language:

english

File:

PDF, 157 KB

english, 2018

3

[IEEE 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - Jeju (2018.1.22-2018.1.25)] 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - HLIFT: A high-level information flow tracking method for detecting hardware Trojans

Wang, Chenguang, Cai, Yici, Zhou, Qiang

Year:

2018

Language:

english

File:

PDF, 221 KB

english, 2018

4

[IEEE 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - Jeju (2018.1.22-2018.1.25)] 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) - A conflict-free approach for parallelizing SAT-based de-camouflaging attacks

Wang, Xueyan, Zhou, Qiang, Cai, Yici, Qu, Gang

Year:

2018

Language:

english

File:

PDF, 155 KB

english, 2018

5

[IEEE 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) - Salt Lake City, UT, USA (2018.6.18-2018.6.23)] 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition - Look at Boundary: A Boundary-Aware Face Alignment Algorithm

Wu, Wenyan, Qian, Chen, Yang, Shuo, Wang, Quan, Cai, Yici, Zhou, Qiang

Year:

2018

File:

PDF, 10 KB

2018

6

Time-domain analysis methodology for large-scale RLC circuits and its applications

Zuying Luo, Yici Cai, Sheldon X. -D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu

Journal:

SCIENCE CHINA Information Sciences

Year:

2006

Language:

english

File:

PDF, 872 KB

english, 2006

7

[IEEE 2006 IEEE International Symposium on Circuits and Systems - Island of Kos, Greece (21-24 May 2006)] 2006 IEEE International Symposium on Circuits and Systems - A novel low-power physical design methodology for MTCMOS

Xin Zhao,, Yici Cai,, Qiang Zhou,, Xianlong Hong,

Year:

2006

Language:

english

File:

PDF, 4.84 MB

english, 2006

8

SIAR: Customized real-time interactive router for analog circuits

Yao, Hailong, Yang, Fan, Cai, Yici, Zhou, Qiang, Sham, Chiu-Wing

Journal:

Integration, the VLSI Journal

Year:

2015

Language:

english

File:

PDF, 3.31 MB

english, 2015

9

[IEEE Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Wanchai, Hong Kong (1999.01.21-1999.01.21)] Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - A new global routing algorithm independent of net ordering

Haiyun Bao,, Xianlong Hong,, Yici Cai,

Year:

1999

Language:

english

File:

PDF, 371 KB

english, 1999

10

[IEEE 2011 International Symposium on Quality Electronic Design (ISQED) - Santa Clara, CA, USA (2011.03.14-2011.03.16)] 2011 12th International Symposium on Quality Electronic Design - A novel fine-grain track routing approach for routability and crosstalk optimization

Qi, Zhongdong, Zhou, Qiang, Jia, Yanming, Cai, Yici, Li, Zhuoyuan, Yao, Hailong

Year:

2011

Language:

english

File:

PDF, 173 KB

english, 2011

11

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - A Global Interconnect Optimization Algorithm under Accurate Delay Model Using Solution Space Smoothing

Yici Cai,, Yibo Wang,, Xianlong Hong,

Year:

2005

Language:

english

File:

PDF, 400 KB

english, 2005

12

[IEEE ISCAS 2003. International Symposium on Circuits and Systems - Bangkok, Thailand (25-28 May 2003)] Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. - Arbitrary convex and concave rectilinear block packing based on corner block list

Yuchun Ma,, Xianlong Hong,, Sheqin Dong,, Yici Cai,, Song Chen,, Chung-Kuan Cheng,, Jun Gu,

Year:

2003

Language:

english

File:

PDF, 319 KB

english, 2003

13

[IEEE 2014 IEEE International Symposium on Circuits and Systems (ISCAS) - Melbourne VIC, Australia (2014.6.1-2014.6.5)] 2014 IEEE International Symposium on Circuits and Systems (ISCAS) - A register clustering algorithm for low power clock tree synthesis

Deng, Chao, Cai, Yici, Zhou, Qiang

Year:

2014

Language:

english

File:

PDF, 714 KB

english, 2014

14

[IEEE Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - Wanchai, Hong Kong (1999.01.21-1999.01.21)] Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) - A timing-driven block placer based on sequence pair model

Gang Huang,, Xianlong Hong,, Changge Qiao,, Yici Cai,

Year:

1999

Language:

english

File:

PDF, 410 KB

english, 1999

15

[IEEE 2005 IEEE International Symposium on Circuits and Systems - Kobe, Japan (23-26 May 2005)] 2005 IEEE International Symposium on Circuits and Systems - Zero Skew Clock Routing with Tree Topology Construction Using Simulated Annealing Method

Xinjie Wei,, Yici Cai,, Xianlong Hong,

Year:

2005

Language:

english

File:

PDF, 195 KB

english, 2005

16

[IEEE 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Liberec, Czech Republic (2009.04.15-2009.04.17)] 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems - Fast congestion-aware timing-driven placement for island FPGA

Jinpeng Zhao,, Qiang Zhou,, Yici Cai,

Year:

2009

Language:

english

File:

PDF, 259 KB

english, 2009

17

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Algorithm for yield driven correction of layout

Yang Wang,, Yici Cai,, Xianlong Hong,, Qiang Zhou,

Year:

2004

Language:

english

File:

PDF, 349 KB

english, 2004

18

[IEEE International Conference on Computer Aided Design (ICCAD) - San Jose, CA, USA (5-9 Nov. 2000)] IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140) - Corner block list: an effective and efficient topological representation of non-slicing floorplan

Xianlong Hong,, Gang Huang,, Yici Cai,, Jiangchun Gu,, Sheqin Dong,, Chung-Kuan Cheng,, Jun Gu,

Year:

2000

Language:

english

File:

PDF, 565 KB

english, 2000

19

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Quick and effective buffered legitimate skew clock routing

Meng Zhao,, Xinjie Wei,, Yici Cai,, Xianlong Hong,

Year:

2004

Language:

english

File:

PDF, 241 KB

english, 2004

20

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration

Changqi Yang,, Xianlong Hong,, Honghua Yang, H., Qiang Zhou,, Yici Cai,, Yonqiang Lu,

Year:

2004

Language:

english

File:

PDF, 235 KB

english, 2004

21

[IEEE 4th International Conference on ASIC - Shanghai, China (23-25 Oct. 2001)] ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) - VLSI/PCB placement with predefined coordinate alignment constraint based on sequence pair

Rui Liu,, Xianlong Hong,, Sheqin Dong,, Yici Cai,, Jun Gu,

Year:

2001

Language:

english

File:

PDF, 296 KB

english, 2001

22

[IEEE 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013) - Yokohama (2013.1.22-2013.1.25)] 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC) - Performance bound and yield analysis for analog circuits under process variations

Xue-Xin Liu,, Palma-Rodriguez, A. A., Rodriguez-Chavez, S., Tan, Sheldon X.-D, Tlelo-Cuautle, E., Yici Cai,

Year:

2013

Language:

english

File:

PDF, 4.19 MB

english, 2013

23

[IEEE 2004 IEEE International Symposium on Circuits and Systems - Vancouver, BC, Canada (23-26 May 2004)] 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) - Layer assignment algorithm for RLC crosstalk minimization

Bin Liu,, Yici Cai,, Qiang Zhou,, Xianlong Hong,

Year:

2004

Language:

english

File:

PDF, 222 KB

english, 2004

24

[IEEE 2006 IEEE International Symposium on Circuits and Systems - Island of Kos, Greece (21-24 May 2006)] 2006 IEEE International Symposium on Circuits and Systems - Performance and Power Aware Buffered Tree Construction

Yibo Wang,, Yici Cai,, Xianlong Hong,

Year:

2006

Language:

english

File:

PDF, 1.84 MB

english, 2006

25

[IEEE 4th International Conference on ASIC - Shanghai, China (23-25 Oct. 2001)] ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549) - The selection and creation of the rules in rules-based optical proximity correction

Rui Shi,, Yici Cai,, Xianlong Hong,, Weimin Wu,, Changqi Yang,

Year:

2001

Language:

english

File:

PDF, 320 KB

english, 2001

26

[IEEE 2006 IEEE International Symposium on Circuits and Systems - Island of Kos, Greece (21-24 May 2006)] 2006 IEEE International Symposium on Circuits and Systems - A novel technique integrating buffer insertion into timing driven placement

Lijuan Luo,, Qiang Zhou,, Yici Cai,, Xianlong Hong,, Yibo Wang,

Year:

2006

Language:

english

File:

PDF, 421 KB

english, 2006

27

[IEEE 2010 International Conference on Communications, Circuits and Systems (ICCCAS) - Chengdu, China (2010.07.28-2010.07.30)] 2010 International Conference on Communications, Circuits and Systems (ICCCAS) - A parasitic extraction method of VLSI interconnects for pre-route timing analysis

Weibing Gong,, Wenjian Yu,, Yongqiang Lu,, Qiming Tang,, Qiang Zhou,, Yici Cai,

Year:

2010

Language:

english

File:

PDF, 203 KB

english, 2010

28

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - Leakage power optimization for clock network using dual-Vth technology

Weixiang Shen,, Yici Cai,, Xianlong Hong,

Year:

2008

Language:

english

File:

PDF, 171 KB

english, 2008

29

[IEEE 2007 IEEE International Symposium on Circuits and Systems - New Orleans, LA, USA (2007.05.27-2007.05.30)] 2007 IEEE International Symposium on Circuits and Systems - Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building

Wang, Yanfeng, Zhou, Qiang, Hong, Xianlong, Cai, Yici

Year:

2007

Language:

english

File:

PDF, 240 KB

english, 2007

30

[ACM Press the 17th great lakes symposium - Stresa-Lago Maggiore, Italy (2007.03.11-2007.03.13)] Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 - New timing and routability driven placement algorithms for FPGA synthesis

Zhuo, Yue, Li, Hao, Zhou, Qiang, Cai, Yici, Hong, Xianlong

Year:

2007

Language:

english

File:

PDF, 189 KB

english, 2007

31

[IEEE 2015 6th Asia Symposium on Quality Electronic Design (ASQED) - Kula Lumpur, Malaysia (2015.8.4-2015.8.5)] 2015 6th Asia Symposium on Quality Electronic Design (ASQED) - An efficient buffer sizing algorithm for clock trees considering process variations

Deng, Chao, Cai, Yici, Zhou, Qiang, Chen, Zhuwei

Year:

2015

Language:

english

File:

PDF, 403 KB

english, 2015

32

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - Module placement with boundary constraints using O-tree representation

Rui Lu,, Xianlong Hong,, Sheqin Dong,, Yici Cai,, Jun Gu,, Chung-Kuan Cheng,

Year:

2002

Language:

english

File:

PDF, 320 KB

english, 2002

33

[IEEE ISCAS 2003. International Symposium on Circuits and Systems - Bangkok, Thailand (25-28 May 2003)] Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. - Evaluating a bounded slice-line grid assignment in O(nlogn) time

Song Chen,, Xianlong Hong,, Sheqin Dong,, Yuchun Ma,, Yici Cai,, Chung-Kuan Cheng,, Jun Gu,

Year:

2003

Language:

english

File:

PDF, 486 KB

english, 2003

34

[IEEE 2007 IEEE International Symposium on Circuits and Systems - New Orleans, LA, USA (2007.05.27-2007.05.30)] 2007 IEEE International Symposium on Circuits and Systems - Effective Acceleration of Iterative Slack Distribution Process

Wei, Xinjie, Cai, Yici, Hong, Xianlong

Year:

2007

Language:

english

File:

PDF, 163 KB

english, 2007

35

[IEEE 2002 IEEE International Symposium on Circuits and Systems - Phoenix-Scottsdale, AZ, USA (26-29 May 2002)] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353) - A standard-cell placement algorithm of optimizing multiple objects

Wenting Hou,, Xianlong Hong,, Weimin Wu,, Yici Cai,

Year:

2002

Language:

english

File:

PDF, 339 KB

english, 2002

36

[IEEE 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - Montréal, QC, Canada (2016.5.22-2016.5.25)] 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - An efficient framework for configurable RO PUF

Chen, Zhuwei, Cai, Yici, Zhou, Qiang, Qu, Gang

Year:

2016

Language:

english

File:

PDF, 467 KB

english, 2016

37

[IEEE 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - Montréal, QC, Canada (2016.5.22-2016.5.25)] 2016 IEEE International Symposium on Circuits and Systems (ISCAS) - Is the Secure IC camouflaging really secure?

Wang, Xueyan, Zhou, Qiang, Cai, Yici, Qu, Gang

Year:

2016

Language:

english

File:

PDF, 607 KB

english, 2016

38

Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips

Wang, Qin, Xu, Yue, Zuo, Shiliang, Yao, Hailong, Ho, Tsung-Yi, Li, Bing, Schlichtmann, Ulf, Cai, Yici

Journal:

IEEE Transactions on Biomedical Circuits and Systems

Year:

2017

Language:

english

File:

PDF, 2.85 MB

english, 2017

39

[IEEE 2017 IEEE 35th International Conference on Computer Design (ICCD) - Boston, MA (2017.11.5-2017.11.8)] 2017 IEEE International Conference on Computer Design (ICCD) - Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans

Wang, Chenguang, Cai, Yici, Zhou, Qiang

Year:

2017

Language:

english

File:

PDF, 250 KB

english, 2017

40

[IEEE 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Baltimore, MD, USA (2017.5.28-2017.5.31)] 2017 IEEE International Symposium on Circuits and Systems (ISCAS) - Cell spreading optimization for force-directed global placers

Wang, Xueyan, Cai, Yici, Zhou, Qiang

Year:

2017

Language:

english

File:

PDF, 719 KB

english, 2017

41

[IEEE 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) - Salt Lake City, UT, USA (2018.6.18-2018.6.23)] 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition - Look at Boundary: A Boundary-Aware Face Alignment Algorithm

Wu, Wenyan, Qian, Chen, Yang, Shuo, Wang, Quan, Cai, Yici, Zhou, Qiang

Year:

2018

Language:

english

File:

PDF, 10 KB

english, 2018

42

An efficient quadratic placement based on search space traversing technology

Yongqiang Lu, Xianlong Hong, Qiang Zhou, Yici Cai, Jun Gu

Journal:

Integration, the VLSI Journal

Year:

2007

Language:

english

File:

PDF, 689 KB

english, 2007

43

Large scale P/G grid transient simulation using hierarchical relaxed approach

Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan

Journal:

Integration, the VLSI Journal

Year:

2008

Language:

english

File:

PDF, 473 KB

english, 2008

44

Partitioning-based decoupling capacitor budgeting via sequence of linear programming

Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong

Journal:

Integration, the VLSI Journal

Year:

2007

Language:

english

File:

PDF, 380 KB

english, 2007

45

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm

Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, Bing Lu

Journal:

Integration, the VLSI Journal

Year:

2008

Language:

english

File:

PDF, 737 KB

english, 2008

46

Optimization of via distribution and stacked via in multi-layered P/G networks

Yici Cai, Jin Shi, Shuai Li

Journal:

Integration, the VLSI Journal

Year:

2010

Language:

english

File:

PDF, 1.20 MB

english, 2010

47

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai

Journal:

Integration, the VLSI Journal

Year:

2010

Language:

english

File:

PDF, 579 KB

english, 2010

48

Floorplanning with abutment constraints based on corner block list

Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu

Journal:

Integration, the VLSI Journal

Year:

2001

Language:

english

File:

PDF, 278 KB

english, 2001

49

An efficient hierarchical timing-driven Steiner tree algorithm for global routing

Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu

Journal:

Integration, the VLSI Journal

Year:

2003

Language:

english

File:

PDF, 425 KB

english, 2003

50

Incremental placement-based clock network minimization methodology

Zhou, Qiang, Cai, Yici, Huang, Liang, Hong, Xianlong

Journal:

Tsinghua Science & Technology

Year:

2008

Language:

english

File:

PDF, 126 KB

english, 2008